Primer

VeriSilicon Primer

VeriSilicon Microelectronics (Shanghai) Co., Ltd. (688521.SH) is a Shanghai-listed, fabless semiconductor IP and one-stop custom-chip design house operating under its proprietary "Silicon Platform as a Service" (SiPaaS) model. Revenue comes from two main lines — semiconductor IP licensing (royalties and license fees on its GPU, NPU, VPU, DSP, ISP and display IPs, plus 1,700+ analog, mixed-signal, RF and interface IPs) and one-stop chip customization (project-based design, integration, tape-out and turnkey manufacturing coordination for fabless customers, OEMs, hyperscalers and IDMs). Founded in 2001 and listed on the Shanghai STAR Market in August 2020, the company has roughly 2,000 employees across nine R&D centers and eleven sales offices worldwide.

Five-Year Price Trajectory

Shares traded in a roughly ¥40-80 band for the first four years after the 2020 IPO, then re-rated sharply through 2025 and into 2026 alongside an AI-driven order surge — up 202% over the trailing 52 weeks against a 52-week range of ¥81.10 – ¥296.96. Implied price points before late 2024 are reconstructed from disclosed market-cap snapshots (Yahoo Finance, finance.yahoo.com/quote/688521.SS).

Revenue And Operating Margin

Revenue compounded from ¥1.5B in 2020 to a record ¥3.15B in 2025 (+35.8% YoY), but profitability inverted starting 2023 as R&D spend stepped up — operating losses have widened to roughly ¥465-530M annually since 2024. Gross margin held near 33% on a trailing-twelve-month basis through Q1 2026, with the bleed concentrated below the gross line.

Business In One Page

What it sells. Two intertwined offerings: (1) Semiconductor IP licensing — six in-house "processing IP" families (GPU, NPU, VPU, DSP, ISP, Display) plus a 1,700+ block library of analog, mixed-signal, RF and interface IPs, monetized via upfront license fees and per-unit royalties; (2) One-stop chip customization (SiPaaS) — full-turnkey services covering RTL-to-GDSII design, verification, foundry/mask coordination, packaging, test and post-silicon software, paid as milestone-based engineering fees with downstream wafer/test margin attached.

Customers. Fabless semiconductor companies, integrated device manufacturers (IDMs), system OEM/ODMs, automotive Tier-1s, and increasingly large internet companies and cloud-service providers commissioning custom AI ASICs. Cumulative shipments of customer chips integrated with VeriSilicon's GPU IP exceed 2 billion units worldwide; NPU IP is in nearly 200 million AI-enabled chips.

Geography and footprint. Headquartered in Shanghai, with R&D centers across China (Shanghai-Zhangjiang, Shanghai-Lin-gang, Beijing, Chengdu, Nanjing, Haikou, Guangzhou) plus Dallas/San Jose (US) and Ho Chi Minh City (Vietnam). Eleven sales offices include the US, Japan, Korea, Germany, France, Taiwan and Hong Kong. The vast majority of revenue is realized through Chinese customers, but a meaningful share of design-IP royalties tracks global semiconductor unit volumes.

Economics. Gross margin runs in the low-30s percent range, reflecting a mix between high-margin IP royalties and lower-margin pass-through turnkey/wafer revenue. R&D investment is the dominant cost driver — Q1 2026 R&D alone was ¥485M, or 58% of quarterly revenue — and is what currently keeps the company in operating loss despite scale. Order backlog has stayed elevated at multi-billion-yuan levels for ten consecutive quarters, providing forward revenue visibility but also explaining why operating leverage has yet to materialize.

Strategic positioning. Ranked No. 1 in mainland China for IC design service revenue and No. 1 for China semiconductor IP revenue. Pushing a "IP as a Chiplet / Chiplet as a Platform / Platform as an Ecosystem" framework to address AIGC and autonomous-driving demand for System-in-Package architectures, with first design wins on 4nm FinFET and 22nm FD-SOI.

What Changed Recently

• Q1 2026 revenue more than doubled YoY to ¥835.7M (+114.47%), driven by both IP licensing and one-stop chip customization; full-year 2025 revenue had already hit a record ¥3.15B, up 35.8% (Quartr earnings summary; Yahoo Finance 688521.SS).
• Order intake stepped up materially — new orders signed between January and April 29, 2026 totaled ¥8.24B, the majority from one-stop chip customization and AI computing power projects (Quartr Q1 2026 summary).
• Backlog mix is heavily AI/data-processing weighted — over 56% of orders on hand are tied to data-processing applications, primarily cloud-side AI ASIC and IP, signaling a structural pivot toward AI workloads.
• Capital raise completed in 2025 — private A-share placement raised RMB 1.81B, contributing to a ¥2.61B FY2025 cash inflow from financing and lifting total assets ~67% to ¥7.72B (Investing.com 688521 financial summary).
• Operating losses continue to widen relative to history — net loss attributable to shareholders deepened to ¥-340.8M in Q1 2026 (vs. ¥-181.1M prior quarter) as R&D spend grew 53% YoY to ¥485M, or 58% of revenue (Quartr Q1 2026 summary).
• Stock has re-rated dramatically — shares are up 202% over the trailing 52 weeks, market cap has expanded from ¥26B at end-2024 to ¥138B currently, and the float now trades at ~38x trailing sales (Yahoo Finance 688521.SS key statistics).

Valuation Snapshot

The market is treating VeriSilicon as a high-growth China AI infrastructure name rather than a profitable IP licensor. At ~38× trailing sales and ~44× book it screens richly versus global IP-licensing peers (ARM trades closer to 35-45× sales, Cadence/Synopsys nearer 12-18×), but the ¥5.13B order backlog and >100% revenue growth in Q1 2026 are doing the heavy lifting in the narrative. Trailing P/E of ~487 is largely an artifact of small positive trailing earnings periods rolling off; on TTM net income (-¥648M) the company is loss-making and a forward multiple is not meaningful. Analyst consensus 12-month target sits at ¥194 (Investing.com), implying ~23% downside from the current ¥252.60 — a sign the rally has run ahead of sell-side models.

Risks And Watchpoints

• Persistent operating losses with widening R&D intensity. R&D was 58% of Q1 2026 revenue. The company has been loss-making at the operating level in three of the last four years, and operating cash flow remains negative (¥-310M TTM). Continued spend without margin recovery would force further dilution.
• Backlog conversion risk. Headline orders of ¥5.13B on hand and ¥8.24B of YTD new orders only matter if they convert at expected margins. Watch quarterly revenue recognition pace versus the 90% "expected to convert within a year" claim, and whether mix shift toward turnkey chip customization compresses gross margin (already down 6.76pp YoY to 32.3% in Q1).
• Valuation re-rating risk. Shares at ~38× TTM sales discount near-flawless execution. Any miss on order intake, gross margin recovery, or AI ASIC ramp could prompt a sharp de-rating, especially with the consensus price target ¥58 below the current quote.
• US-China semiconductor export controls. VeriSilicon's design-IP and turnkey services depend on foundry access (including advanced nodes) and on foreign-origin IP/EDA inputs. Tightening US restrictions on advanced-node access for China-based chip designers, or specific entity-list action, could materially impair the high-end AI ASIC franchise driving current growth.
• Customer concentration and AI cycle exposure. Over 56% of order book is data-processing/AI applications. A pull-back in Chinese hyperscaler AI capex, or in-house IP development by major customers, would hit growth disproportionately.
• Governance/structure. Weighted voting rights structure concentrates control among the founding shareholder group (VeriSilicon Limited holds ~15.1% economically but with enhanced voting), and insiders own ~22% — public investors have limited say on strategic direction.
• Funding and dilution. With negative free cash flow (-¥571M levered FCF TTM) and total debt of ¥1.82B, future equity raises remain a real possibility. The 2025 ¥1.81B placement is a precedent.